This application claims priority to Korean Application No. 2000-4250, filed Jan. 28, 2000, the disclosure of which is hereby incorporated herein by reference.
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device in which a point in time when a column-type command such as a column address strobe (CAS) command is input can be varied from a point in time when a row-type command such as a row address strobe (RAS) command is input.
2. Description of the Related Art
A The input and output operations of semiconductor memory devices are generally controlled by combination of a plurality of signals. For example, the data input and output operations of semiconductor memory devices are controlled by a chip select signal (hereinafter, referred to as a CS signal), a column address strobe signal (hereinafter, referred to as a CAS signal), and a write enable signal (hereinafter, referred to as a WE signal). Also, semiconductor memory devices receive the CS signal, the CAS signal and the WE signal via pins connected to the outside. The CS signal, the CAS signal and the WE signal received via the external pins are buffered by buffers.
Synchronous DRAMs operate in synchronization with an external clock signal which is input externally to the synchronous DRAMs. Also, the synchronous DRAMs, in which the CS signal, the CAS signal and the WE signal are input to and combined in corresponding buffers, generate signals associated with reading and writing in synchronization with the external clock signal.
The synchronous DRAMs receive row-type commands and then column-type commands such as the CS signal, the CAS signal and the WE signal. However, conventional synchronous DRAMs require at least a command delay time, a so-called xe2x80x98tRCDmin (RAS to CAS)xe2x80x99, between the input of a row-type command and the input of a column-type command. That is, in conventional synchronous DRAMs, column-type commands are received after a period of xe2x80x98tRCDxe2x80x99 after row activation starts in response to received row-type commands, since data input and output is not possible until memory cells connected to a row selected after a row command is input share charge and detect charge.
That is, conventional synchronous DRAMs have a limit in unavoidably requiring a time interval of tRCDmin between a point in time when a row-type command is received and a point in time when a column-type command is received.
An object of the present invention is to provide a semiconductor memory device in which the time interval between a point in time when a row-type command is received and a point in time when a column-type command is received can be shorter than a predetermined minimum time interval tRCDmin.
Another object of the present invention is to provide a buffer and a signal transmission circuit which are applied to the semiconductor memory device.
To achieve the first object, there is provided a semiconductor memory device including a mode set register, a /CAS buffer, a /CS buffer and a /WE buffer. The mode set register can program the delay time from when a row address strobe (RAS) command is input to when a column address strobe (CAS) command is input, and provides a plurality of control signals. In the mode set register, one among the plurality of control signals is activated corresponding to the delay time. The /CAS buffer receives and buffers a predetermined /CAS signal. In the /CAS buffer, the /CAS signal is delayed for a predetermined number of delay clock cycles in response to the control signal. The /CS buffer receives and buffers a predetermined /CS signal. In the /CS buffer, the /CS signal is delayed for the number of delay clock cycles in response to the control signal. The /WE buffer receives and buffers a predetermined /WE signal. In the /WE buffer, the /WE signal is delayed for the number of delay clocks in response to the control signal.
To achieve the second object, there is provided a buffer for a semiconductor memory device having a mode register set circuit, including a signal transmission unit for delaying a received signal for a predetermined number of delay clock cycles and transmitting the received signal, wherein the number of delay clock cycles is determined in response to predetermined control signals which are generated from the mode register set circuit.
To achieve the second object, there is provided a signal transmission circuit for transmitting a received signal, including a plurality of transmission units each having a different number of delay clock cycles, for delaying and transmitting the received signal. At least one of the transmission units includes: a transmission switch for transmitting the received signal in response to a corresponding control signal; and a clock delay unit which is enabled in response to the control signal, and delays a signal received from the transmission switch for the delay clock cycles and transmits the delayed signal in response to a predetermined clock signal.
According to a semiconductor memory device of the present invention, the time for which a column-type command is delayed after a row-type command is received can be reduced.